找高手帮身为大学生的我设计一个VHDL程序～～～～本人在此先谢谢了！！！！

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_UNSIGNED.all;
entity updncount16en is
port (
clk: in STD_LOGIC;
dir: in STD_LOGIC;
clr: in STD_LOGIC;
en: in STD_LOGIC;
q0: out STD_LOGIC;
q1: out STD_LOGIC;
q2: out STD_LOGIC;
q3: out STD_LOGIC;
STD_LOGIC
);
end updncount16en;
architecture updncount16en_arch of updncount16en is
signal(3 downto 0);
begin
q0<=count_4(0);
q1<=count_4(1);
q2<=count_4(2);
q3<=count_4(3);
process(clk,clr)
begin
if(clr='1')then
count_4<="0000";
elsif(clk'event and clk='1')then
if(en='1')then
if(dir='1')then
if(count_4="1111")then
count_4<="0000";
cao<='1';
else
count_4<=count_4+'1';
cao<='0';
end if;
elsif(dir='0')then
if(count_4="0000")then
count_4<="1111";
cao<='1';
else
count_4<=count_4-'1';
cao<='0';
end if;
end if;
end if;
end if;
end process;
end updncount16en_arch;