芯片原厂必学技术之脚本篇（10）基于 Python、Shell 脚本和 Verilog、C 语言的文件比较环境搭建（数字 IC 验证）

        这是基于 Python、Shell 脚本、Verilog、C 语言、UVM 方法搭建的一个文件数据自动对比的环境，能够实现 Verilog 模块的输出和 C 模型的输出的自动数据对比，达到一个高效的、自动化的、自动定位的数字 IC 验证效果~

        目前已经应用于芯片公司简单的 UT 模块验证中，不需要通过 UVM 环境和 SV 语言，就能够实现大批数据量的自动对比，这是数字 IC 设计者和脚本设计者的福音~

#!/bin/bash
#This Script ...

echo "The Comparision Result is: "
i=(
00 01 02)
j=(
04 05 06)
for(k=0;k<=2;k=k+1)
do

cd ./riscv_core_old/run
sed -i "1101c ${j[$k]}" llram.hex
./run

cd ./riscv_core_new/run
sed -i "1101c ${j[$k]}" llram.hex
./run

cd ../../
python3 cmp.py

#diff ./riscv_core_old.txt ./riscv_core_new.txt
#if ["$?" == "0"]; then
#	echo "right"
#else
#	echo "different"
#fi
done
#gcc test.c
#./a.out

import operator
import numpy as np

riscv_core_verilog = []
riscv_core_cmodels = []

#import v & c data
with open("./riscv_core_v.txt", "r") as aaa_: #import verilog data
    aaa__ = [line.strip() for line in aaa_]
    
with open("./riscv_core_c.txt", "r") as bbb_: #import c model data
    bbb__ = [line.strip() for line in bbb_]
    
#looking for the num of data comparision
for i in range(0, N):
    riscv_core_verilog.append(aaa__[i])
    riscv_core_cmodels.append(bbb__[i])

#mem compare results
print('nn', "0. The Total Number of Comparision is: ")
print("***********************************************")
print("**********", len(riscv_core_verilog), "*********")
print("***********************************************")

print('n', "1. The " "ENCRYPT" " Comparision Result is: ")
if(operator.eq(riscv_core_verilog, riscv_core_cmodels)
and (len(riscv_core_verilog) == len(riscv_core_cmodels))):
    print("*******************************************")
    print("************* MEM COMPARE PASS ************")
    print("*******************************************")
else:
    print("*******************************************")
    print("************* MEM COMPARE FAIL ************")
    print("*******************************************")

int      N = 10000, i, j;
FILE *fpr1 = fopen("riscv_core_data_i.dat", "r");
FILE *fpw1 = fopen("riscv_core_data_o.dat", "w");

//read
int a[N];
for(i=0;i 
四、基于 Verilog HDL 的文件读写 
// ------------------------------
// SpyGlass/VCS/Verdi/DC
// Shell/Perl/Python/Makefile/TCL
// C/MATLAB/SV/UVM
// ------------------------------

// Verdi:
initial begin
	#500000;
	$finish(2);
end
initial begin
	$fsdbDumpfile("wave_000.fsdb");
	$fsdbDumpvars;
	$vcdpluson;
end

// Verdi(2d mem add wave):
initial begin
    $fsdbDumpfile("wave_000.fsdb");
    $fsdbDumpvars(0, "instance=", "testbench");
    $fsdbDumpMDA (0, "instance=", "testbench");
    #500000
    $fsdbDumpoff;
    $finish(1);
end

// Timescale:
`timescale 1ns/100ps //unit and accuracy.
`include "define.v"
module tb_riscv_core();

// RTL Signal:
`define ADDR_BUS 31:0
`define WRITE_ENABLE 1'b1
wire [`ADDR_BUS] m0_addr;
assign addr = (mem_we == `WRITE_ENABLE) ? wr_addr : rd_addr;
wire [`ADDR_BUS] m0_addr = u_riscv_core.u_if.m0_addr;

// Readmemb($) & Readmemh($):
reg [31:0] mem [31:0];
initial begin
	$readmemb("./init_mem.coe", mem); //$readmemh.
end

// B2B(read data from file):
`define MEM_DEPTH 4096
parameter WAIT_FOR_START = 81;
parameter CLOCK_PERIOD   = 40;
reg [31:0] mem [`MEM_DEPTH-1:0];
reg [15:0] mem_addr = 15'b0;
integer file;
integer i, s;
initial begin
	file = $fopen("./init_mem.coe", "r");
	for(i=0;i<`MEM_DEPTH;i=i+1) begin
		s = $fscanf(file, "%d", mem[i]);
	end
	$fclose(file);
	if(`MEM_DEPTH != 0)
		$display("sram initialization success");
	else
		$display("sram empty");
end
initial begin
	#WAIT_FOR_START;
	repeat(`MEM_DEPTH) begin
		din = $signed(mem[mem_addr]);
		mem_addr = mem_addr + 1;
		#CLOCK_PERIOD;
	end
end

// B2B(write data to file):
integer file;
initial begin
	file = $fopen("./init_mem.coe", "w");
	#500000;
	$fclose(file);
end
always @(posedge clk or negedge rst_n) begin
	if(in_vld)
		$fwrite(file, "%dn", dout);
end