八.国民技术MCU开发之 XFMC模块之PSRAM

• 八.国民技术MCU开发之 XFMC模块之PSRAM
• • 1.相关开发环境
  • 2. MCU PSRAM 硬件原理图
  • 3.PSRAM 初始化以及读写测试代码
  • • 3.1 XFMC_Psram_Init
    • • 3.1.1 XFMC RCC时钟使能
      • 3.1.2 XFMC 配置Block 以及MemType
    • 3.2 PSRAM读写 函数XFMC_Psram_Write_Buffer

硬件版本：N32G457QEL_EVB V1.1

软件SDK版本 Nationstech.N32G45x_Library.1.1.1

开发软件：KEIL

    uint8_t bank_index  = 1;
    uint16_t tx_buffer[BUFFER_SIZE];
    uint16_t rx_buffer[BUFFER_SIZE];
int psram_test_main(void)
{


    uint32_t wr_status = 0;

    //Debug_USART_Config();
    printf("rnxfmc external 16bit psram test startrn");

    //while(bank_index < TEST_SRAM_NUM)
    {
				 printf("rnbank_index=%drn",bank_index);
        
        XFMC_Psram_Init(bank_index);
								 printf("rnbank_index=%d %drn",bank_index,__LINE__);
        
        XFMC_Psram_Fill(bank_index,WRITE_READ_ADDR, BUFFER_SIZE, 0xFFFF);
								 printf("rnbank_index=%d %drn",bank_index,__LINE__);
        
        Fill_Buffer(tx_buffer, BUFFER_SIZE, 0x1230);
								 printf("rnbank_index=%d %drn",bank_index,__LINE__);
        
        XFMC_Psram_Write_Buffer(tx_buffer, bank_index, WRITE_READ_ADDR, BUFFER_SIZE);
								 printf("rnbank_index=%d %drn",bank_index,__LINE__);
        
        Memset((void *)rx_buffer,0,BUFFER_SIZE*2);
        
        
        XFMC_Psram_Read_Buffer(rx_buffer, bank_index, WRITE_READ_ADDR, BUFFER_SIZE);
								 printf("rnbank_index=%d %drn",bank_index,__LINE__);
        
        wr_status = Buffercmp(tx_buffer, rx_buffer, BUFFER_SIZE);

        if (wr_status == PASSED)
        {
            
            printf("xfmc psram_%d read and write test passrn",bank_index);
        }
        else
        {
            
            printf("xfmc psram_%d read and write test failrn",bank_index);
        }

//        bank_index++;
    }

//    while (1)
//    {
//    }
}

        
        XFMC_Psram_Init(bank_index);

void XFMC_Psram_Init(uint8_t bank_num)
{
    XFMC_Bank1_Block *bank_index;
    XFMC_NorSramInitTpye XFMC_NORSRAMInitStructure;
    XFMC_NorSramTimingInitType readWriteTiming;
    bank_index = bank_num == 0 ? XFMC_BANK1_BLOCK1 : XFMC_BANK1_BLOCK2;

    
    RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_XFMC, ENABLE);
    
    SRAM_Gpio_Config(bank_num);

    readWriteTiming.AddrSetTime      = XFMC_NOR_SRAM_ADDR_SETUP_TIME_3HCLK;
    readWriteTiming.AddrHoldTime     = XFMC_NOR_SRAM_ADDR_HOLD_TIME_1HCLK;
    readWriteTiming.DataSetTime      = XFMC_NOR_SRAM_DATA_SETUP_TIME(0x05);
    readWriteTiming.BusRecoveryCycle = XFMC_NOR_SRAM_BUSRECOVERY_TIME_8HCLK;
    readWriteTiming.ClkDiv           = XFMC_NOR_SRAM_CLK_DIV_2;
    readWriteTiming.DataLatency      = XFMC_NOR_SRAM_DATA_LATENCY_2CLK;
    readWriteTiming.AccMode          = XFMC_NOR_SRAM_ACC_MODE_A;

    XFMC_NORSRAMInitStructure.Block            = bank_index;
    XFMC_NORSRAMInitStructure.DataAddrMux      = XFMC_NOR_SRAM_MUX_DISABLE;
    XFMC_NORSRAMInitStructure.MemType          = XFMC_MEM_TYPE_PSRAM;
    XFMC_NORSRAMInitStructure.MemDataWidth     = XFMC_NOR_SRAM_DATA_WIDTH_16B;
    XFMC_NORSRAMInitStructure.BurstAccMode     = XFMC_NOR_SRAM_BURST_MODE_DISABLE;
    XFMC_NORSRAMInitStructure.AsynchroWait     = XFMC_NOR_SRAM_ASYNC_NWAIT_DISABLE;
    XFMC_NORSRAMInitStructure.WaitSigPolarity  = XFMC_NOR_SRAM_WAIT_SIGNAL_LOW;
    XFMC_NORSRAMInitStructure.WrapMode         = XFMC_NOR_SRAM_WRAP_DISABLE;
    XFMC_NORSRAMInitStructure.WaitSigConfig    = XFMC_NOR_SRAM_NWAIT_BEFORE_STATE;
    XFMC_NORSRAMInitStructure.WriteEnable      = XFMC_NOR_SRAM_WRITE_ENABLE;
    XFMC_NORSRAMInitStructure.WaitSigEnable    = XFMC_NOR_SRAM_NWAIT_DISABLE;
    XFMC_NORSRAMInitStructure.ExtModeEnable    = XFMC_NOR_SRAM_EXTENDED_DISABLE;
    XFMC_NORSRAMInitStructure.WriteBurstEnable = XFMC_NOR_SRAM_BURST_WRITE_DISABLE;
    XFMC_NORSRAMInitStructure.RWTimingStruct   = &readWriteTiming;
    XFMC_NORSRAMInitStructure.WTimingStruct    = &readWriteTiming;

    XFMC_InitNorSram(&XFMC_NORSRAMInitStructure);
    XFMC_EnableNorSram(bank_index, ENABLE);
}

根据原理图用了NE2，所以是XFMC_BANK1_BLOCK2，

即参数 uint8_t bank_index = 1;

RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_XFMC, ENABLE);

XFMC_NORSRAMInitStructure.Block            = bank_index;
XFMC_NORSRAMInitStructure.DataAddrMux      = XFMC_NOR_SRAM_MUX_DISABLE;
XFMC_NORSRAMInitStructure.MemType          = XFMC_MEM_TYPE_PSRAM;

void XFMC_Psram_Write_Buffer(uint16_t* pBuffer, uint8_t bank_index, uint32_t write_addr, uint32_t number)
{
    uint32_t transfer_addr;
    transfer_addr = bank_index == 0 ? Bank1_SRAM1_ADDR : Bank1_SRAM2_ADDR;
    for (; number != 0; number--) 
    {
        while(1)
        {
            
            *(__IO uint16_t*)(transfer_addr + write_addr) = *pBuffer;

            
            if(*(__IO uint16_t*)(transfer_addr + write_addr) == *pBuffer)
                break;
        }

        
        pBuffer++;
        write_addr += 2;
    }
}

#define Bank1_SRAM1_ADDR ((uint32_t)0x60000000) // 0x60000000~63FFFFFF
#define Bank1_SRAM2_ADDR ((uint32_t)0x64000000) // 0x64000000~67FFFFFF
#define Bank1_SRAM3_ADDR ((uint32_t)0x68000000)

INDEX=1 用的是Bank1_SRAM2_ADDR

0. // 0x60000000~63FFFFFF
   #define Bank1_SRAM2_ADDR ((uint32_t)0x64000000) // 0x64000000~67FFFFFF
   #define Bank1_SRAM3_ADDR ((uint32_t)0x68000000)

INDEX=1 用的是Bank1_SRAM2_ADDR