C++：Lock-free

lock free__GCC_ATOMIC_BOOL_LOCK_FREEHAVE_sync_compare_and_swapqiHAVE_atomic_compare_and_swapqiIntel x86 提供的cmpxchg命令

意思就是，不使用锁，而实现原子操作。
libstdc+±v3/libsupc++/atomic_lockfree_defines.h
可以用的是gcc里提供的各个基本类型的无锁操作。

#if __cplusplus >= 201103L
#define ATOMIC_BOOL_LOCK_FREE		__GCC_ATOMIC_BOOL_LOCK_FREE
#define ATOMIC_CHAR_LOCK_FREE		__GCC_ATOMIC_CHAR_LOCK_FREE
#define ATOMIC_WCHAR_T_LOCK_FREE	__GCC_ATOMIC_WCHAR_T_LOCK_FREE
#define ATOMIC_CHAR16_T_LOCK_FREE	__GCC_ATOMIC_CHAR16_T_LOCK_FREE
#define ATOMIC_CHAR32_T_LOCK_FREE	__GCC_ATOMIC_CHAR32_T_LOCK_FREE
#define ATOMIC_SHORT_LOCK_FREE		__GCC_ATOMIC_SHORT_LOCK_FREE
#define ATOMIC_INT_LOCK_FREE		__GCC_ATOMIC_INT_LOCK_FREE
#define ATOMIC_LONG_LOCK_FREE		__GCC_ATOMIC_LONG_LOCK_FREE
#define ATOMIC_LLONG_LOCK_FREE		__GCC_ATOMIC_LLONG_LOCK_FREE
#define ATOMIC_POINTER_LOCK_FREE	__GCC_ATOMIC_POINTER_LOCK_FREE
#endif

看看这个是什么？cpp_atomic_builtins 函数定义的

builtin_define_with_int_value ("__GCC_ATOMIC_BOOL_LOCK_FREE", (have_swap[SWAP_INDEX (boolean_type_node)]? 2 : 1)); 、、 根据是否有swap操作，对于此类型，如果有就是2 无就是1

if (HAVE_sync_compare_and_swapqi || HAVE_atomic_compare_and_swapqi)
{
cpp_define (pfile, “__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1”);
have_swap[1] = true;
}
上面的判断需要看HAVE_sync_compare_and_swapqi 或者 HAVE_atomic_compare_and_swapqi这两个值

gcc在定义这个变量时的栈结构
#0  cpp_define (pfile=0x2b70220, str=0x1e006a8 "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1") at ../.././libcpp/directives.c:2442
#1  0x00000000008fdcfc in cpp_atomic_builtins (pfile=0x2b70220) at ../.././gcc/c-family/c-cppbuiltin.c:645
#2  0x00000000009002e5 in c_cpp_builtins (pfile=0x2b70220) at ../.././gcc/c-family/c-cppbuiltin.c:1367
#3  0x000000000091b401 in c_finish_options () at ../.././gcc/c-family/c-opts.c:1400
#4  0x000000000091ac59 in c_common_parse_file () at ../.././gcc/c-family/c-opts.c:1141
#5  0x0000000000fce6e9 in compile_file () at ../.././gcc/toplev.c:455
#6  0x0000000000fd1209 in do_compile () at ../.././gcc/toplev.c:2160
#7  0x0000000000fd14f0 in toplev::main (this=0x7fffffffe2ae, argc=2, argv=0x7fffffffe3a8) at ../.././gcc/toplev.c:2295
#8  0x0000000001c8eb3b in main (argc=2, argv=0x7fffffffe3a8) at ../.././gcc/main.c:39

这个值是怎么来的？ 一直没找到。在HPPA中有定义这个值，X86里没看到。所以x86架构，不是用这个变量来标识。

x86 环境使用这个宏
sync.md

(define_expand "atomic_compare_and_swap"
  [(match_operand:QI 0 "register_operand")	;; bool success output
   (match_operand:SWI124 1 "register_operand")	;; oldval output
   (match_operand:SWI124 2 "memory_operand")	;; memory
   (match_operand:SWI124 3 "register_operand")	;; expected input
   (match_operand:SWI124 4 "register_operand")	;; newval input
   (match_operand:SI 5 "const_int_operand")	;; is_weak
   (match_operand:SI 6 "const_int_operand")	;; success model
   (match_operand:SI 7 "const_int_operand")]	;; failure model
  "TARGET_CMPXCHG"   、、、、目标是否提供 cmpxchg
{
  emit_insn
   (gen_atomic_compare_and_swap_1
    (operands[1], operands[2], operands[3], operands[4], operands[6]));
  ix86_expand_setcc (operands[0], EQ, gen_rtx_REG (CCZmode, FLAGS_REG),
		     const0_rtx);
  DONE;
})

CMPXCHG (compare and exchange) 和CMPXCHG8B (compare and exchange 8 bytes) 可以用了在多处理器的系统上做同步原语。CMPXCHG 指令需要三个操作数：
a source operand in a register, 一个寄存器，是源
another source operand in the EAX register, 另一个操作数是EAX操作数，也是源
and a destination operand. 目的操作数
如果目标操作数的值和EAX寄存器的值对比，发现相等，就将第一个操作数的值存到目的操作数中。如果不相等，目的操作数据的值会放到EAX中。
The status flags in the EFLAGS register reflect the result that would have been obtained by subtracting the destination operand from the value in the EAX register.
The CMPXCHG instruction is commonly used for testing and modifying semaphores. It checks to see if a semaphore is free. If the semaphore is free, it is marked allocated; otherwise it gets the ID of the current owner. This is all done in one uninterruptible operation. In a single-processor system, the CMPXCHG instruction eliminates the need to switch to protection level 0 (to disable interrupts) before executing multiple instructions to test and modify a semaphore. For multiple processor systems, CMPXCHG can be combined with the LOCK prefix to perform the compare and exchange operation atomically. (See “Locked Atomic Operations” in Chapter 8, “Multiple-Processor Management,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information on atomic operations.)
The CMPXCHG8B instruction also requires three operands: a 64-bit value in EDX:EAX, a 64-bit value in ECX:EBX, and a destination operand in memory. The instruction compares the 64-bit value in the EDX:EAX registers with the destination operand. If they are equal, the 64-bit value in the ECX:EBX registers is stored in the destination operand. If the EDX:EAX registers and the destination are not equal, the destination is loaded in the EDX:EAX registers. The CMPXCHG8B instruction can be combined with the LOCK prefix to perform the operation atomically.