之前实验存个档
源程序：
module count(clk,reset,en,load,up_down,q,count,d );
input clk,reset,en,load,up_down;
//clk时钟信号;复位端reset;en使能端;load预制数控制端;up_down增减计数控制端
//reset低电平，输出清零
//en高电平对输出进行赋值
//load高电平，输入d的值在clk上升沿存入计数器寄存器reg_in
//up_down低电平加法计数器，高电平减法计数器
input [3:0] d; //输入
output reg [3:0] q; //输出
output count; // B/C
reg [3:0] reg_in; //寄存器
reg count;
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
q=0;
count=0;
end
else if(reset)
begin
if (load)
begin
q=d;
count=0;
end //reg_in==q?
else if (~load)
begin
if(en)
begin
if(!up_down)
begin
if (q<8)
begin
q=q+1;
count=0;
end
else if (q==8)
begin
q=q+1;
count=1;
end
else if (q==9)
begin
q=0;
count=0;
end
end
else
begin
if(q>1)
begin
q=q-1;
count=0;
end
else if(q==1)
begin
q=q-1;
count=1;
end
else if(q==0)
begin
q=9;
count=0;
end
end
end
end
end
end
endmodule
激励文件：
module sim_count( );
reg clk,reset,en,load,up_down;
reg [3:0]d;
wire count;
wire [3:0]q;
count uut(.clk(clk),.reset(reset),.en(en),.load(load),.up_down(up_down),.d(d),.count(count),.q(q));
initial
begin
clk=0;reset=1;en=1;load=1;up_down=0;d=5;
end
always #1 clk=~clk;
always #3 en=~en;
always #250 reset=~reset;
always //load周期500ns
begin
#100 load=~load; //0~100ns load=1
#400 load=~load; //100~400ns load=0
end
always #500 up_down=~up_down;
//always #600 d=d+1;
endmodule
