基于FPGA的步进电机驱动

module stepper_motor(
    clk, 
    rst, 
    Dir, 
    start_end_key,
    speed_up_key,
    speed_down_key,
    StepDrive
    );
    input           clk;//50M时钟信号 
    input           rst; //复位信号，低电平有效
    input           Dir; //方向控制信号
    input           start_end_key; // 开始暂停控制信号
    input           speed_up_key; // 控制信号
    input           speed_down_key; // 控制信号
    
    output[3:0]     StepDrive; 
    
    reg[3:0]        StepDrive;
    reg[2:0]        state; 
    reg[31:0]       StepCounter; 
    reg[31:0]       StepLockOut ;//250HZ
    // reg[31:0] StepLockOut = 32'd2;//只用于仿真
    // 此处的数值为200000，因为实验中所使用的晶振时钟频率是50MHz，
    // 这样我们为步进电机提供了250Hz的频率，使之能正常工作。 

    
    // 功能：按键消抖
    // 说明：
    // ***********************************************************
    wire speed_up_key_out;
    wire speed_down_key_out;
    wire start_end_key_out;
    wire Dir_key_out;

    key     key_1(
        .clk        (clk),
        .reset_n    (rst),
        .key        (speed_up_key),
        .key_en_out (speed_up_key_out)
        );
    key     key_2(
        .clk        (clk),
        .reset_n    (rst),
        .key        (speed_down_key),
        .key_en_out (speed_down_key_out)
        );
    key     key_3(
        .clk        (clk),
        .reset_n    (rst),
        .key        (Dir),
        .key_en_out (Dir_key_out)
        );
    key     key_4(
        .clk        (clk),
        .reset_n    (rst),
        .key        (start_end_key),
        .key_en_out (start_end_key_out)
        ); 

// 功能：按键消抖
// 说明：
    // 对按键进行计数，计数范围也就是电机速度的档位范围，档位范围为1~10
    // 所以计数的范围为1~10。该计数结果主要用于对PWM的脉冲宽度进行控制和用于
    // 显示在数码管上。
// ***********************************************************
    reg [3:0] key_cnt;
    always @(posedge clk or negedge rst)
    begin
        if(rst == 1'b0)
        begin
            key_cnt <= 4'd0;
        end 
        else
        begin
            if(!speed_up_key)//判断按键是否按下
            begin
                if(key_cnt == 4'd9)
                    key_cnt <= 4'd0;
                else
                    key_cnt <= key_cnt + 1'b1;
            end
            else if(!speed_down_key_out)
            begin
                if(key_cnt == 4'd0)
                    key_cnt <= 4'd9;
                else
                    key_cnt <= key_cnt - 1'b1;
            end
            else
            begin
                key_cnt <= key_cnt;
            end
        end 
    end
    always @(posedge clk or negedge rst)
    begin
        if(rst == 1'b0)
        begin
            // key_counter_ge <= 4'd1;//初始状态下，直流电机速度设置为档位5
            // key_counter_shi <= 4'd0;
            StepLockOut <= 32'd205000;
        end 
        else
        begin
            case(key_cnt)
            4'd0:begin StepLockOut <= 32'd209000;end
            4'd1:begin StepLockOut <= 32'd208000;end
            4'd2:begin StepLockOut <= 32'd207000;end
            4'd3:begin StepLockOut <= 32'd206000;end
            4'd4:begin StepLockOut <= 32'd205000;end
            4'd5:begin StepLockOut <= 32'd204000;end
            4'd6:begin StepLockOut <= 32'd203000;end
            4'd7:begin StepLockOut <= 32'd202000;end
            4'd8:begin StepLockOut <= 32'd201000;end
            4'd9:begin StepLockOut <= 32'd200000;end
            default:begin StepLockOut <= 32'd200000;end
            endcase
        end 
    end

// 功能： 启动与暂停
// 说明：
// ***********************************************************
reg [1:0]start_state;
reg start_signal;
always @(posedge clk or negedge rst)
begin
    if(!rst)
    begin
        start_state<= 2'b01;
        start_signal <= 1'b0;
    end
    else
    begin
        case (start_state)
        2'b01:
        begin
            start_signal <= 1'b0;
           if(!start_end_key_out)
           begin
                start_state<= 2'b11;
           end
           else
           begin
                start_state<= 2'b01;
           end
        end
        2'b11:
        begin
            start_signal <= 1'b1;
           if(!start_end_key_out)
           begin
                start_state<= 2'b01;
           end
           else
           begin
                start_state<= 2'b11;
           end
        end
        default:
        begin
            start_state<= 2'b01;
            start_signal <= 1'b0;
        end
        endcase
    end
end

// 功能： 方向控制
// 说明：
// ***********************************************************
reg [1:0]   dri_state;
reg         dri_signal;
always @(posedge clk or negedge rst)
begin
    if(!rst)
    begin
        dri_state<= 2'b01;
        dri_signal <= 1'b0;
    end
    else
    begin
        case (dri_state)
        2'b01:
        begin
            dri_signal <= 1'b0;
           if(!Dir_key_out)
           begin
                dri_state<= 2'b11;
           end
           else
           begin
                dri_state<= 2'b01;
           end
        end
        2'b11:
        begin
            dri_signal <= 1'b1;
           if(!Dir_key_out)
           begin
                dri_state<= 2'b01;
           end
           else
           begin
                dri_state<= 2'b11;
           end
        end
        default:
        begin
            dri_state<= 2'b01;
            dri_signal <= 1'b0;
        end
        endcase
    end
end   

// 功能： pwm产生模块
// 说明：
// ***********************************************************
    always @(posedge clk or negedge rst)
    begin 
        if(!rst)    
        begin 
            StepDrive <= 4'd0;
            state <= 3'd0;
            StepCounter <= 32'd0;
        end
        else  
        begin
            if(start_signal == 1'b1)
            begin
                StepCounter <= StepCounter + 1'b1; 
                if (StepCounter >= StepLockOut)
                begin
                    StepCounter <= 32'b0; 
                    if (dri_signal == 1'b1)           
                        state <= state + 1'b1 ;// 选择正转
                    else if (dri_signal == 1'b0)       
                        state <= state - 1'b1 ; //选择反转
                    case (state)
                        3'b000 : StepDrive <= 4'b0001 ; 
                        3'b001 : StepDrive <= 4'b0011 ; 
                        3'b010 : StepDrive <= 4'b0010 ; 
                        3'b011 : StepDrive <= 4'b0110 ; 
                        3'b100 : StepDrive <= 4'b0100 ; 
                        3'b101 : StepDrive <= 4'b1100 ; 
                        3'b110 : StepDrive <= 4'b1000 ; 
                        3'b111 : StepDrive <= 4'b1001 ;  
                    endcase 
                end
            end
        end     
    end
endmodule

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提取码：1234