- 生成mako模板
- 生成json文件
- 创建python脚本来生成DC综合脚本
- 参考文章
在设计中DC综合都是按照一定流程进行的，所以大部分内容不会被改变，在这里首先生成一个DC综合脚本的mako模板，并命名为“dc_template”。该模板中的"&{----}"都为可修改的参数部分。
##### set library and path #####
set lib_path ${lib_path}
set lib_file ${lib_file}
set symlib_path ${symlib_path}
set symlib_file ${symlib_file}
set search_path [concat $search_path $lib_path]
set target_libray [list $lib_file]
set link_library [list * $lib_file]
set symbol_library [list $symlib_path/$symlib_file]
##### detect latch #####
define_name_rules VLSI_NET -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type net -max_length 256
define_name_rules VLSI_CELL -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type net -max_length 256
define_name_rules VLSI_PORT -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type net -max_length 256
define_name_rules TAN_RULE -allowed "a-zA-Z0-9_" -first_restricted "0-9_[]" -max_lendth 256 -map {{{"*cell", "mycell"}，{"*-return","myreturn"}}};
set hdlin_check_no_latch
##### read_verilog #####
% for rtl in rtls:
read_verilog ${rtl}
%endfor
current_design ${top_name}
link
uniquify
##### constraint set #####
set auto_wire_load_selection true
set_wire_load_mode top
creat_clock -name ${clk_name} -period ${clk_period} [get_ports ${clk_name}]
set_clock_latency -source ${clk_latency} ${clk_name}
set_ideal_network [all_clocks]
set_ideal_network [get_ports ${rst_name}]
set_clock_uncertainty &{clk_uncertain} -setup [all_clocks]
set_input_delay ${max_input_delay} -max -clock ${clk_name} [remove_from_collection [all_inputs] {${rst_name} ${clk_name}}
set_input_delay ${min_input_delay} -min -clock ${clk_name} [remove_from_collection [all_inputs] {${rst_name} ${clk_name}}
set_output_delay ${max_output_delay} -max -clock ${clk_name} [all_outputs]
set_output_delay ${min_output_delay} -min -clock ${clk_name} [all_outputs]
set_max_area ${max_area}
set_max_fanout ${max_fanout} [get_designs ${top_name}]
set_max_transition ${max_transition} [get_designs ${top_name}]
set_drive ${drive} [all_inputs]
set_load ${load} [all_outputs]
set_fix_multiple_port_nets -all -buffer_constants
##### compile #####
compile -map_effort medium -boundary_optimization
##### report #####
remove_unconnected_ports [get_cells -hier {*}]
change_names -hierarchy -rules TAN_RULE
report_timing -delay max -max_paths ${max_timing_path > [list ${rpt_dir}/${top_name}_timing.rpt]}
report_area > [list ${rpt_dir}/${top_name}_area.rpt]
report_constrain -all_violators -verbose > [list ${rpt_dir}/${top_name}_constrain.rpt ]
##### generate sdc and netlist file #####
change_name -rule verilog -hier
write -format verilog -hierarchy -output [list ${top_name}_netlist.v]
write_sdc [list ${top_name}.sdc]
生成json文件
完成mako模板设计后，为了配置模板中的参数（&{----}）,所以需要生成一个json文件，并命名位"syn.json"。即在这里将所有需要配置的参数放入到json文件中进行配置。(冒号后面参数为自己需要配置的参数)
{
"lib_path" :"library path",
"lib_file" :"xxxxx.sdb",
"symlib_path" :"symbol library path",
"symlib_file" :"xxxxx.sdb",
"rtl_path" :"rtl code path",
"rtl_file" :"rtl file list:rtl.flist",
"rpt_dir" :"report save path",
"top_name" :"design top module name",
"netlist" :"netlist save path",
"sdc_file" :"sdc save path",
"clk_name" :"clock name",
"clk_period" :"clock period",
"clk_latency" :"clock latency",
"clk_uncertain" :"clock uncertainty",
"rst_name" :"reset name",
"max_input_delay" :"max input delay",
"min_input_delay" :"min input delay",
"max_output_delay" :"max output delay",
"min_output_delay" :"min output delay",
"max_timing_path" :"max timing path"，
"max_area" :"max area",
"max_fanout" :"max fanout",
"max_transition" :"max transition",
"max_capcitance" :"max capacitance",
"drive" :"drive",
"load" :"load"
}
创建python脚本来生成DC综合脚本
import os
import json
from mako.template import Template
#### config ####
jsonfile = open('syn.json').read()
cfg = json.loads(jsonfile)
print(cfg)
lib_path = cfg["lib_path"]
lib_file = cfg["lib_file"]
symlib_path = cfg["symlib_path"]
symlib_file = cfg["symlib_file"]
rtl_path = cfg["rtl_path"]
rtl_file = cfg["rtl_file"]
rpt_dir = cfg["rpt_dir"]
top_name = cfg["top_name"]
netlist = cfg["netlist"]
sdc_file = cfg["sdc_file"]
clk_name = cfg["clk_name"]
clk_period = cfg["clk_period"]
clk_latency = cfg["clk_latency"]
clk_uncertain = cfg["clk_uncertain"]
rst_name = cfg["rst_name"]
max_input_delay = cfg["max_input_delay"]
min_input_delay = cfg["min_input_delay"]
max_output_delay = cfg["max_output_delay"]
min_output_delay = cfg["min_output_delay"]
max_timing_path = cfg["max_timing_path"]
max_area = cfg["max_area"]
max_fanout = cfg["max_fanout"]
max_transition = cfg["max_transition"]
max_capacitance = cfg["max_capacitance"]
drive = cfg["drive"]
load = cfg["load"]
rtls = open(rtl_file,'r').read().splitlines()
print(rtls)
print('Generate syn.tcl ...')
t = open('mako.template','r').read()
mytemplate = Template(t)
scr = mytemplate.render(
lib_path = lib_path ,
lib_file = lib_file ,
symlib_path = symlib_path ,
symlib_file = symlib_file ,
rtl_path = rtl_path ,
rtl_file = rtl_file ,
rpt_dir = rpt_dir ,
top_name = top_name ,
netlist = netlist ,
sdc_file = sdc_file ,
clk_name = clk_name ,
clk_period = clk_period ,
clk_latency = clk_latency ,
clk_uncertain = clk_uncertain ,
rst_name = rst_name ,
max_input_delay = max_input_delay ,
min_input_delay = min_input_delay ,
max_output_delay = max_output_delay ,
min_output_delay = min_output_delay ,
max_timing_path = max_timing_path ,
max_area = max_area ,
max_fanout = max_fanout ,
max_transition = max_transition ,
max_capacitance = max_capacitance ,
drive = drive ,
load = load ,
rtls = rtls)
tcl = open('syn.tcl','w')
tcl.write(scr)
print('Complete the DC script')
参考文章
参考文章
http://exasic.com/article/index.php?md=py-35
