10.5 design a mealy FSM

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 

    parameter data0 = 0, data1 = 1, data2 = 2;
    reg [1:0] state, next;
    
    always @(*) begin
        case (state)
            data0 : next = x? data1 : data0;
            data1 : next = x? data1 : data2;
            data2 : next = x? data1 : data0;
        endcase
    end
    
    always @(posedge clk or negedge aresetn) begin
        if (!aresetn) 
            state <= data0;
        else
            state <= next;
    end
    
    assign z = (state == data2 & x)? -1 : 0;  // The output of Mealy FSM depends both on 
                                             //state and input;  
    
endmodule