verilog 中编译错误：port must be connected to a structural net exp

verilog 中编译错误：port must be connected to a structural net expressionmodule counter8(clk,clr,te,le,a,tf);input clk,te,le,clr;input [7:0] a;output [7:0] tf;reg [7:0] tf,th;regth u1(le,a,th);count u2(clk,clr,te,th,tf);endmodulemodule regth(le,a,thout);input le;input [7:0] a;output [7:0] thout;reg[7:0] thout;always@(le)beginif(le==1) thout